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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:05:21 12/02/2009 
-- Design Name: 
-- Module Name:    ALU - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
    Port ( function_code : in  STD_LOGIC_VECTOR (2 downto 0);
           RegA : in  STD_LOGIC_VECTOR (15 downto 0);
           RegB : in  STD_LOGIC_VECTOR (15 downto 0);
           result : out  STD_LOGIC_VECTOR (15 downto 0);
			  zero : out  STD_LOGIC;
           carry : out  STD_LOGIC);
end ALU;



architecture Behavioral of ALU is

	--signal carryr : STD_LOGIC_VECTOR (16 downto 0);

begin	

--	with function_code select
--		carryr <= RegA + RegB when "000",
--					 RegA and RegB when "001",
--					 RegA nor RegB when "010",
--					 RegA or RegB when "011",
--					 RegA - RegB when "100",
--					 RegA xor RegB when "101",
--					 "00000000000000000" when others;
	 
	process(function_code, RegA, RegB)
	variable temp : STD_LOGIC_VECTOR (15 downto 0);
	begin
		case function_code is
			when "000" => temp := RegA + RegB;
			when "001" => temp := RegA and RegB;
			when "010" => temp := RegA nor RegB;
			when "011" => temp := RegA or RegB;
			when "100" => temp := RegA - RegB;
			when "101" => temp := RegA xor RegB;
			when others => null;
		end case;
		if RegA(15)='1' and RegB(15)='1' then carry <= '1';
		else carry <= '0';
		end if;
	 --carry <= carryr(16);
	 --with carryr(15 downto 0) select
	--	zero <= '1' when "0000000000000000",
	--			  '0' when others;
		case temp is
			when "0000000000000000" => zero <= '1';
			when others => zero <= '0';
		end case;
		result <= temp;
	end process;
		


end Behavioral;

library IEEE;
use IEEE.std_logic_1164.all;

package mips_ALU is
	component ALU
		Port ( function_code : in  STD_LOGIC_VECTOR (2 downto 0);
				RegA : in  STD_LOGIC_VECTOR (15 downto 0);
				RegB : in  STD_LOGIC_VECTOR (15 downto 0);
				result : out  STD_LOGIC_VECTOR (15 downto 0);
				zero : out  STD_LOGIC;
				carry : out  STD_LOGIC);
	end component;
end mips_ALU;